Oldest pages
Appearance
Showing below up to 50 results in range #51 to #100.
- 4.0 Data Structures Algorithms (DSA) (13:31, 8 July 2025)
- 4.1 Data Structures (13:34, 8 July 2025)
- 10.0 Artificial Intelligence (AI) & Machine Learning (14:21, 8 July 2025)
- 10.1 Introduction to AI (14:29, 8 July 2025)
- 10.1.2 Applications of AI (14:37, 8 July 2025)
- 10.2 Types of Machine Learning (14:54, 8 July 2025)
- 10.2.1 Supervised Learning (Regression, Classification) (15:12, 8 July 2025)
- 10.2.2 Unsupervised Learning (Clustering, Dimensionality Reduction) (15:22, 8 July 2025)
- 10.2.3 Reinforcement Learning (15:27, 8 July 2025)
- 10.5 Natural Language Processing (NLP) / Computer Vision (CV) (15:39, 8 July 2025)
- 10.5.1 Basic tasks and applications (15:46, 8 July 2025)
- 10.5.2 Large Language Models (LLMs) (16:03, 8 July 2025)
- 10.5.2.1 Generative Pre-trained Transformers (GPT) (16:38, 8 July 2025)
- 10.3 Common ML Algorithms (17:22, 8 July 2025)
- 10.3.1 Linear Regression, Logistic Regression (17:33, 8 July 2025)
- 10.3.2 Decision Trees, Random Forests (17:57, 8 July 2025)
- 10.3.3 Support Vector Machines (SVM) (18:18, 8 July 2025)
- 10.3.4 K-Means Clustering (18:55, 8 July 2025)
- 10.4 Neural Networks & Deep Learning (Basic Concepts) (19:18, 8 July 2025)
- 10.4.1 Perceptrons, Layers (19:33, 8 July 2025)
- 10.4.2 Activation Functions (19:55, 8 July 2025)
- 13.5 Ethical AI & Societal Impact (23:03, 8 July 2025)
- 4.1.1 Linear Data Structures (14:09, 9 July 2025)
- 4.1.1.2 Linked Lists (Singly, Doubly, Circular) (14:22, 9 July 2025)
- 4.1.1.3 Stacks (LIFO) (14:30, 9 July 2025)
- 4.1.1.4 Queues (FIFO, Priority Queues) (14:37, 9 July 2025)
- 4.1.2 Non-Linear Data Structures (14:42, 9 July 2025)
- 4.1.2.1 Trees (Binary Trees, Binary Search Trees, AVL Trees, Red-Black Trees) (14:51, 9 July 2025)
- 4.1.2.2 Graphs (Directed, Undirected, Weighted) (15:35, 9 July 2025)
- 4.1.2.3 Hash Tables (Hashing Functions, Collision Resolution) (15:49, 9 July 2025)
- 4.1.2.4 Heaps (Min-Heap, Max-Heap) (15:52, 9 July 2025)
- 5.0 Computer Architecture & Organization (16:40, 9 July 2025)
- 5.1 CPU Components (17:15, 9 July 2025)
- 5.1.1 Arithmetic Logic Unit (ALU) (17:20, 9 July 2025)
- 5.1.2 Control Unit (CU) (17:42, 9 July 2025)
- 5.1.3 Registers (17:49, 9 July 2025)
- 5.1.4 Instruction Cycle (Fetch, Decode, Execute, Store) (17:57, 9 July 2025)
- 5.2 Memory Hierarchy (18:10, 9 July 2025)
- 5.2.1 Cache Memory (L1, L2, L3) (18:19, 9 July 2025)
- 5.2.2 RAM (Random Access Memory) (18:26, 9 July 2025)
- 5.2.3 ROM (Read-Only Memory) (18:40, 9 July 2025)
- 5.2.4 Virtual Memory (Basic Concept) (18:49, 9 July 2025)
- 5.3 Input/Output Systems (19:13, 9 July 2025)
- 5.3.1 I/O Devices and Controllers (19:49, 9 July 2025)
- 5.3.2 Polling, Interrupts, DMA (20:08, 9 July 2025)
- 5.4 Instruction Sets (20:42, 9 July 2025)
- 5.4.1 RISC vs. CISC (21:09, 9 July 2025)
- 5.5 Assembly Language (Basic Concepts) (21:34, 9 July 2025)
- 4.2 Algorithms (21:51, 9 July 2025)
- 4.2.1 Sorting Algorithms (21:53, 9 July 2025)